tm-096 integrated stratum 3e timing solution product brief the tm-096 integrated timing module is based on a digital pll that performs ltering of the selected input signal and then synchronizes the signal to an onboard stratum 3e ocxo. the synchronized signal is then passed through an analog pll with an integrated vcxo in order to deliver 3 high quality output signals. con guration and monitoring of the module s operation is achieved via an spi interface. the operating modes of the tm-096 include: 1) free-run, 2) holdover, and 3) locked. in the free-run mode the timing module loc ks to the on- board ocxo. in the holdover mode, the tm-096 generates outputs based upon its most recent input signal lock history. for the locked mode, the dpll locks onto one of 8 input reference clocks. selection of the reference can be automatic or manual. the tm-096 supports both master and slave operation. a typical application for the tm-096 would include two modules whereby on e unit is con gured as a master clock and the other serves as a backup or redundant clock. a number of external hardware pins are provided for con guration and alarm purposes. the tm-096 is also equipped with a jtag interface for factory programming and testing. single module for stratum 3e clock synchronization complies with telcordia/itu-t recommendations free-run, holdover, and locked operating modes accepts 8 reference inputs generates 3 output clocks hit-less reference switching master or slave con guration supports serial peripheral interface (spi) ieee 1149.1 jtag standard test access port single 3.3v operation 2.05 x 1.25 x 0.76 package size rohs/lead free compliant multiservice switches/routers add/drop multiplexers (adms) ip and atm core switches sonet/sdh dwdm synchronous ethernet features applications block diagram vectron international ?267 lowell road, hudson, nh 03051 ?tel: 1-88-vectron-1 ?http://www.vectron.com reference monitor and selection cpu dpll ocxo apll 1 output dividers and synthesizers ex ref 1 ex ref 2 ex ref 3 ex ref 4 ex ref 5 ex ref 6 ex ref 7 ex ref 8 ms_ref ms reset sync_clk sync_8k los lol ho_det bits_clk apll 2 bits_s spi jtag sdi sdo sclk ss tdi tdo tck tms sint prelimina performs t ltering of the selected input signal and then syn ng of the selected input signal l is then passed through an analog pll with an integrated v hrough an analog pll with onitoring of the module?s operation is achieved via an spi in e module?s operation is achieve ee-run, 2) holdover, and 3) locked. in the free-run mode the e-run, 2) holdover, and 3) locked. in the free- 096 generates outputs based upon its most recent input sig 096 generates outputs based upon its most re ence clocks. selection of the reference can be automatic o ce clocks. selection of the reference can be aster and slave operation. a typical application for the tm-0 peration. a typical application ock and the other serves as a backup or redundant clock. her serves as a backup or redun ternal hardware pins are provided for cont guration and ala re pins are provided for cont gur ogramming and testing. ramming and testing pre pplications rev. 1
vectron international ?267 lowell road, hudson, nh 03051 ?tel: 1-88-vectron-1 ?http://www.vectron.com parameter speci cations voltage +3.3 vdc power <1 a during warm up, < 500 ma steady state input signals number of input references 8 reference 1-8 frequency range 8khz - 77.76mhz signal level lvcmos time reference characteristics telcordia: gr-1244-core 3.2.1. r3-1 output signals number of output signals 3 output 1 (sync_clk) 1.544 to 77.76mhz output 2 (sync_8k) 8khz output 3 (bits_clk) 1.544 or 2.048mhz signal level lvcmos input and output reference signal characteristics input signal telcordia: gr-1244-core 3.2.1 jitter tolerance telcordia: gr-1244-core 4.2, gr-253-core 5.4.4.3.6 phase transient tolerance telcordia: gr-1244-core 4.4 wander generation telcordia: gr-1244-core 5.3, gr-253-core 5.4.4.3.2 wander tolerance telcordia: gr-1244-core 4.3 wander transfer telcordia: gr-1244-core 5.3, gr-253-core 5.4.4.2.4 mtie telcordia: gr-1244-core 5.3, gr-253-core 5.4.4.3.2 tdev telcordia: gr-1244-core 5.3, gr-253-core 5.4.4.3.2 phase transients telcordia: gr-1244-core 5.6, gr-253-core 5.4.4.3.3 jitter generation telcordia: gr-1244-core 5.5, gr-253-core 5.6.2.3 jitter transfer telcordia: gr-1244-core 5.5, gr-253-core 5.6.2.1 dpll performance free run accuracy ?.6ppm holdover stability ?.2x10 -8 (stratum 3e) pull in range ?7ppm lock time 100s (stratum 3e) lock accuracy 1x10 -11 (average 24hr) speci cations outline drawing prelimina min prelimin prelimi p in in m m min min im im min min im im mi mi lim lim m m lim lim m m elim elim m m eli eli prel prel pre prel pre pre pr pre pr pr p p p p m m m m m m m m m m m m m m m m p p p p p p p p p p p p p p p p p speci cati + 3.3 vd c +3 <1 a during w input sign ut references erence 1-8 frequency range ncy r gnal leve time re f erence characteristic s rence characteristics number o f output signals number of output sig output 1 (sync output 2 (sync_8k) outpu o inary sign inary on rev. 1 3.75 1.100 27.94 .148 .105 2.67 pin 1 .100 2.54 .575 14.61 .025 0.64 .060 1.52 2.100 53.34 1.310 33.27
pin# symbol i/o function 1 los o loss of signal alarm 2 lol o loss of lock alarm 3 ms_ref i master/slave reference input 4 ref1 i reference input signal 1 5 ref2 i reference input signal 2 6 ref3 i reference input signal 3 7 ref4 i reference input signal 4 8 tdi i jtag test data input 9 tms i jtag test mode select 10 trst i jtag test reset 11 bits_clk o output 3 - synchronous bits clock (either 1.544 or 2.048 mhz) 12 sync_8k o output 2 - synchronous mast/slave 8 khz clock 13 sync_clk o output 1 - synchronous primary clock 14 nc no connect 15 ref5 i reference input signal 5 16 ref6 i reference input signal 6 17 ref8 i reference input signal 8 18 ref7 i reference input signal 7 19 nc no connect 20 bits_s i bits_clk select input (1 = 1.544mhz, 0 = 2.048mhz) 21 ho_det o holdover detect (1 = holdover available) 22 tdo o jtag test data output 23 tclk i jtag test clock 24 gnd case ground 25 sclk i spi serial clock input 26 sdi i spi serial data input 27 vcc i +3.3 v supply voltage 28 ss i spi slave select (active low enables spi port) 29 reset i tm-096 reset (active low, 10 ms hold time minimum) 30 sdo o spi serial data output 31 sint o spi interrupt (active low) 32 ms i master select (1 = master, 0 = slave) pin out ordering information TM-096-DAC-B-SNNNN* tm-096 = timing module in 2.05 x 1.25 x 0.76 package, d = 3.3v ?%, a = lvcmos output, c = 0?to 70?, b = stratum 3e, snnnn* = unique alpha-numeric code assigned at time of order designating customers output frequencies. please specify out1 (1.544 ?77.76 mhz) and out3 (1.544 or 2.048 mhz). vectron international ?267 lowell road, hudson, nh 03051 ?tel: 1-88-vectron-1 ?http://www.vectron.com disclaimer vectron international reserves the right to make changes to the product(s) and or information contained herein without notice. no liability is assumed as a result of their use or application. no rights under any patent accompany the sale of any such product(s) or information. product status and speci cations are subject to change. preliminary preliminary y y y y y y y y ry ry ry ry ry ry y ry ary ary ry ary ary y ry nary nary ry ina y ina y y y ina ina in in min min min min i i i imi imi li li li l lim lim li l l li li l lim lim li l l li li el lim lim li el el eli eli el lim lim li el el p eli eli el li li li p p p prel prel p el el el l l l p p p p prel pre p el e e l p p p pre pre p e e e p p p p pre pre p e e e p p p pr pr p p p p p p p p p p p p 44 or 2.048 mhz) ronous primary clock re f erence input signal 5 signal 5 e input signal 6 re f erence input signal 8 reference input si eference input signa n o co nne ct no c lk select input (1 = 1.54 o holdover detect (1 = holdover availab over detect ( o j i i jtag tes sc lk i 27 27 v cc vcc i 8 i 29 r e s e t rese i 30 do 3 1 3 s in t int 32 p c version change notes version date note 1.0 11/29/2007 pre-release rev. 1
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